Cadence Design Systems, Inc. (NASDAQ: CDNS) this week unveiled its High-Speed Ethernet Controller IP family, which the company says enables complete, silicon-proven Ethernet subsystem solutions up to 800G, along with the Cadence SerDes PHY IP in 7nm, 5nm and 3nm process nodes.
The new controller family supports different aggregated bandwidths for 100G, 200G, 400G and 800G Ethernet connectivity. The platform offers support for both single- and multi-Ethernet channel systems and compliance with IEEE 802.3 and Ethernet Technology Consortium specifications
Optimized for power, performance and area (PPA), the new low-latency, high-speed controller IP expands Cadence’s Ethernet Controller IP portfolio and is well-suited for a broad array of Ethernet applications in next-generation cloud, artificial intelligence and machine learning (AI/ML), and 5G infrastructures, says the company.
Rishi Chugh, vice president of product marketing, IP Group at Cadence, comments:
“The exploding bandwidth demand from cloud, AI/ML and 5G has driven Ethernet protocols to evolve and has accelerated 800G market adoption. Cadence continues to invest in design and interface IP that addresses our customers’ rapidly evolving requirements.
The Cadence high-speed Ethernet subsystem solutions with best-in-class PHY and feature-rich controller IP further solidify our leadership position with high-performance connectivity IP offerings.”
Cadence adds that a number of customer engagements are underway, and that there is strong market interest in the new product family.
Technical notes
Cadence says the new IP provides full-featured media access control (MAC), physical coding sublayer (PCS), forward error correction (FEC) and physical medium attachment (PMA) blocks for a complete architecture.
Integrated FEC support, including RS(528,514), RS(544,514), Firecode and Ethernet Technology Consortium Low Latency RS FEC, allows customers the flexibility to choose the best option for their application requirements.
Along with Cadence’s 112G/56G and other Ethernet SerDes PHY IP, Cadence provides full subsystem deliveries with integrated PHY and controller that enable customers to ease integration and streamline their SoC designs.
Silicon proven in AI/ML customer applications, the integrated subsystems provide optimal PPA, concludes the firm.
